1. Field of the Invention
The present invention relates to a high power MOS device composed of a plurality of elemental MOS FET's, and more particularly to a monolithic MOS integrated circuit for high power driving (referred to as a high power MOSIC hereinafter) of the kind equipped with protective means against abnormality condition such as overcurrent.
2. Description of the Prior Art
The high power MOSIC is being used widely for ignition control Or brake control of motor vehicles for the reason that it makes the driving and switching of a large current possible, and it is playing an important role for realization of an electronic control system of motor vehicles. A high degree of reliability is fundamentally demanded of the control system for motor vehicles in order to prevent personal accidents. Accordingly, the reliability requirement for each of the electronic components that constitute the electronic control system is severe.
While the required level of reliability is high as mentioned above, the operating environment of the high power MOSIC is a harsh one which is accompanied by variations in the operating voltage caused by electromagnetic induction, variations in the constants of the load, variations due to changes in the temperature, and the like. For these reasons, such a high power MOSIC normally has a built-in protective circuit against these various kinds of variations. Namely, such a high power MOSIC has within the IC sensors which respectively detect an overcurrent in the electronic circuit caused by a short-circuiting generated on the part of the load, an overvoltage accompanying an external electromagnetic induction, and an overheated state of the MOSIC itself, and is so constructed as to prevent the breakdown of the chip as a whole by temporarily suspending the operation of the high power part of the MOSIC in response to the output of these sensors.
The protective circuit disclosed in the specification of U.S. Pat. No. 4,703,390 entitled "Integrated Circuit Power Timer", for example, uses a power MOS FET constructed by connecting a large number of MOS FET's in parallel and detects an overcurrent with one of the large number of MOSFETs that are connected to a load in common, and prevents the breakdown of the MOSIC due to an overcurrent and an overtemperature by reflecting the allowable upper limit of the temperature of the MOSIC chip on a reference voltage which is the comparative object with the output of the MOSFET for overcurrent detection. However, in spite of the fact that such a circuit construction can appropriately detect an overcurrent that is caused by the load alone and lead to the interruption of Operation of the high power MOSFET part, the driving of the high power MOSFET part becomes impossible if a short-circuiting is generated between the gate and the source in one or several units of the parallely-connected large number of MOSFETs. As shown in the specification of the U.S. Patent, the high power MOSFET is normally constituted of parallel connection (the so-called multicell construction) of a large number of MOSFETs each of which consisting of the mutually isolated regions of source, drain and gate, instead of being constituted of a single FET. The reason for doing so is that it is effective for reducing the on-resistance by maintaining the advantages of the MOSFET, namely, a large gain, a high input impedance, facility of securing the balance in the parallel connection state, and the like. However, when a large number of gate electrodes are commonly connected with each other as described in the aforementioned U.S. Patent in order to realize the multicell structure, the on-off control of the load current becomes impossible if a short-circuity is generated between the gate and the source.
It is therefore the object of the present invention to provide a power MOS device composed of a large number of MOS FET's connected in parallel, which maintain its operation even if gate-source short-circuiting is produced in a part of the large number of MOS FET's.
It is another object of the present invention to provide a monolithic power MOSIC including a power MOSFET part of multicell structure which is substantially free from the influence of short-circuiting between the gate and the source of the power MOSFET part.